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RM0008
Advanced-control timers (TIM1&TIM8)
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
2.
3.
4.
5.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 76. Control circuit in external clock mode 2
f CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
13.3.5
Counter register
Capture/compare channels
34
35
36
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 77 to Figure 80 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Doc ID 13902 Rev 9
269/995
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